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IBM z13 Configuration Best Practices

IBM z13 Configuration

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In terms of how a program behaves, for most programs that have been written recently, and/or are recompiled on a regular basis, you probably won’t have any problems. However, there are certain things you should be aware of. An in-depth explanation is available in “IBM z Systems Processor Optimizer Primer,” but one of the things it’s critical to be aware of is not storing near the instruction stream. IBM has been warning against mixing instructions and data for at least 15 years. With separate instruction and data caches, and modern processor design assumptions, such code can be exceptionally inefficient.

Another thing you can control is how busy the CEC is. Again, for availability reasons, IBM recommends against running a CEC 100 percent utilized on a regular basis, but there are also CPU time/transaction impacts to consider as well. Again, because CPUs have outpaced memory and I/O, cache misses take relatively longer to retrieve data for each successive processor generation, and as the CPU gets busier, cache misses are more and more likely. So transactions will take longer, in terms of time spent on the CPU, on a very busy CEC.


To plan your CEC configuration, IBM made available an LPAR Design tool that you can use. Enter information about the CEC and the LPARs defined on the CEC, and it will tell you how many high, medium and low processors of each type each LPAR will have. You can also use the IBM Topology Report tool in conjunction with WLM SMF 99.14 records to see how your CEC is laid out at a given point in time.

With APAR OA48570, IBM introduced SMF 98 records that contain frequently collected, low-level dispatching data indicating system efficiency and its influencers. This is in contrast to most other SMF data, which is mostly summary data over a long reporting intervals. With SMF98 data, you can see information about how efficiently your LPARs are running, and what is influencing that efficiency. There’s a demo that shows the sort of information you can get from SMF98s. Most usefully, IBM developers have been looking at the data to identify patterns that correlate with low system efficiency, and can highlight those areas of time and what can be done to improve system efficiency (e.g., reducing the number of initiators or threads, reducing the use of vertical low CPs or identifying programs that are causing high rates of locking).

Configuration Advantage

This isn’t the first time that the mainframe has gone through a transition like this; in the 1990s, IBM switched from using CPUs built using bipolar transistors to ones using CMOS technology. The reason the switch was made was because bipolar chips run much hotter than CMOS chips. However, CMOS chips were much slower than bipolar chips, so it took several years before CMOS machines had the same capacity as the bipolar machines they were replacing.

Unlike then, there isn’t a new technology we can switch to; but also unlike then, the microarchitectural changes are increasing the capacity of the mainframe dramatically. But if you want to take advantage of everything the mainframe offers, and do so in the most efficient way possible, you may need to think a bit more about how you’re configuring your images.

Anne Romanowski contributed to the technical and editorial review of this article.

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